The present invention relates to the design and testing of power management integrated circuits.
Power amplifiers, low drop-out regulators and voltage regulators are examples of power management integrated circuits that include power transistors. Voltage regulators, such as DC-to-DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC-to-DC converters are particularly needed for battery management in low power devices, such as laptop computers and mobile phones. Switching voltage regulators (or simply xe2x80x9cswitching regulatorsxe2x80x9d) are known to be an efficient type of DC-to-DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage, and filtering the high frequency voltage to generate the output DC voltage.
Conventional synchronous switching regulators include two switches implemented with power transistors. One power transistor is used to alternately couple and decouple an unregulated input DC voltage source, such as a battery, to a load, such as an integrated circuit. The other power transistor is used to alternately couple and decouple the load to ground. An output filter, typically including an inductor and an output capacitor, is coupled between the input voltage source and the load to filter the output of the switches and produce the output DC voltage. The two power transistors are typically controlled by a pulse modulator, such as a pulse width modulator or a pulse frequency modulator.
Performance of a switching regulator is generally affected by the characteristics of the power transistors. When a power transistor is open, it is desirable to-have the power transistor operate as close to an open circuit as possible, i.e., the off-resistance of the power transistor should be very high (ideally infinite). In the closed position, the power transistor should act as a close to a short circuit as possible, i.e., the on-resistance of the power transistor should be very small (ideally zero). A high on-resistance generally results in increased power dissipation in the power transistor, degrading the efficiency of the regulator.
One of the challenges in the design of switching regulators with on-chip power transistors is the testability of the device during manufacturing. As just discussed, it is desireable to minimize the on-resistance of the power transistors. Unfortunately, it is difficult to obtain an accurate measurement reading of a low on-resistance value, e.g., tens of mxcexa9 or lower, because the package lead resistance, the socket resistance or the contact resistance of a probe during a wafer probe test or the automatic test equipment (ATE) contactor""s contact resistance can be of the order of the on-resistance value. To create a voltage drop across the power transistor that is measurable at a required degree of accuracy, a substantially large DC current has to be provided to the power transistor. Recent automatic test equipment (ATE) testers that are designed to handle complex mixed-signal IC testing are typically not equipped with integrated instrumentation to measure complex mixed-signal circuits and support high current conduction simultaneously. In addition, the conduction of a high current through wafer probe tips tends to wear out the hardware very quickly, resulting in production delays and increased testing cost.
Furthermore, to test the closed-loop performance of the regulator using ATE, large currents must be conducted through the ATE, the test probes, and their associated parasitic inductance. Since the parasitic inductance introduced during ATE testing may be an order of magnitude larger than that in the typical application for the regulator, large transient voltages are created on-chip when the power transistors switch, leading to measurement inaccuracies and potentially even permanent damage to the chip.
In one aspect, the invention is directed to a switching regulator having first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals. The controller is operable in a plurality of modes including a normal mode in which the controller opens and closes all of the first transistor segments and all of the second transistor segments, and a test mode in which the controller opens and closes less than all of the first transistor segments and all of the second transistor segments.
Implementations of the invention may include one or more of the following features. Each first transistor segment may have a source coupled to the first terminal, a drain coupled to the first node and a gate coupled to the controller through a segment control line. Each second transistor segment may have a source coupled to the first node, a drain coupled to the second node and a gate coupled to the controller through a segment control line. The controller may operate in the normal mode in response to a substantially constant load. The controller may be configured to switch to the test mode in response to a request to measure an on-resistance of a power transistor. The first power transistor may be a p-channel MOSFET and the second power transistor may be an n-channel MOSFET. All of the segments may have an equivalent transistor width.
In another aspect, the invention is directed to a method for measuring an on-resistance of a power transistor integrated onto an integrated circuit chip. The power transistor includes a plurality of individually-addressable transistor segments. Less than all of the transistor segments are closed, an on-resistance of the closed transistor segments is measured, and an on-resistance of the power transistor is derived from the on-resistances of the transistor segments.
Implementations of the invention may include one or more of the following features. The transistor segments may be closed one at a time, an on-resistance of each closed transistor segment may be measured; and an on-resistance of the power transistor may be derived by averaging the on-resistances of all of the transistor segments. The transistor segments may have an equivalent width. Each transistor segment may include one or more single transistors connected in parallel.
In another aspect, the invention is directed to a method of testing a switching regulator with a power transistor on an integrated circuit chip for use with an application board having circuitry that includes a first inductor with a first inductance and a first capacitor with a first capacitance. In the method, a power transistor including a plurality of individually-addressable transistor segments on a chip is provided. The chip is installed on a testing board having circuitry that includes a second inductor with a second inductance greater than the first inductance and a first capacitor with a second capacitance less than the first capacitance. The circuit is operated with the power transistor on the integrated circuit chip using less than all of the transistor segments, and a closed-loop performance characteristic of the switching regulator is measured.
Implementations of the invention may include one or more of the following features. The performance characteristic may be output voltage, line regulation or load regulation. Measuring the line regulation may include measuring first and second output voltages with different input voltages. Measuring the load regulation may include measuring first and second output voltages with different load currents, e.g., a minimum load current and a modified maximum load current (that is less than a maximum load current for the switching regulator when installed on an application board). The application board may have a first load current, and the test board may have a second load current that is less than the first load current. The chip may be installed on an application board having circuitry that includes the first inductor with the first inductance and the first capacitor with the first capacitance. The power transistor may include N transistor segments, and the operating step may be performed using exactly one of the N transistor segments. The first inductance may be L and the second inductance may be L*N. The first capacitance may be C and the second capacitance may be C/N. An on-resistance of a closed transistor segment may be measured during operation of the circuitry, and an on-resistance of the power transistor may be derived from the on-resistance of the closed transistor segment.
Advantages that can be seen in implementations of the invention include one or more of the following. The resistance of the power transistors in a switching regulator can be measured accurately. The resistance of the power transistors can be controlled more accurately, leading to more precisely control the switching timing. Switching-related losses can be reduced by decreasing the on-resistance of the power transistors.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features and advantages of the invention will become apparent from the description, the drawings, and the claims.